The present invention relates to feedback control systems, and particularly to those feedback systems utilizing phase-locked loops.
Feedback systems are well known in the art and are found in a multitude of different configurations. One such well-known configuration is a phase locked loop (PLL). A generalized block diagram is shown in FIG. 1 of a traditional PLL configured for a clock and data recovery application. Such a configuration may be used for recovering clock and data streams compatible with the SONET specification, as well as others. The phase locked loop 100 includes a phase detector 102 (or alternatively, a phase/frequency detector) which receives the input data signal conveyed on node 112 and receives a data clock signal conveyed on node 122. The phase detector 102 generates on its output node 116 an error signal which is a function of the phase difference (and frequency difference in the case of a phase/frequency detector) between the input data signal and the data clock signal, and often includes data retiming circuitry to generate on an output node 114 the reconstructed data, as shown.
A loop filter 104 filters the output of the phase detector 102 to generate a control voltage signal on node 118 which is provided to a voltage controlled oscillator 110 in order to influence the frequency (and hence the phase) of the VCO output clock signal conveyed on node 120. The loop filter 104 frequently includes an integrator block which is implemented using a charge pump and a loop filter capacitor. The VCO output clock signal may be divided-down by divider 106 to generate the data clock signal (conveyed on node 122) based upon the expected data rate of the incoming data signal.
If such a PLL were implemented using discrete components, precision components could be used to provide a nominal VCO frequency relatively close to a desired center frequency. However, such a discrete implementation is costly and requires a large amount of printed wiring board space, and more than likely would have difficulty achieving the performance required of modem systems while operating at an acceptable power level. Consequently, most VCOs are implemented monolithicly (i.e., on a single integrated circuit die). As is well known in the art, the absolute value of certain parameters on an integrated circuit may vary greatly due to process variations (e.g., lot-to-lot variations, wafer-to-wafer variations within a lot, die-to-die variations within a wafer) and as environmental variables change (e.g., die temperature, power supply voltage variations, etc.). Even though the tracking of certain parameters within a single integrated circuit is frequently quite good (which is the basis of many advantageous circuit techniques), the nominal frequency of many VCO circuits can vary greatly from die to die. While the frequency of the VCO can inherently be adjusted by an appropriate control voltage, the subsequent adjustability of the VCO may be reduced if the control voltage otherwise necessary to achieve the initially-desired VCO frequency falls too close to either the upper extreme or the lower extreme of its range. Said differently, such a PLL 100 may perform more optimally over time when the control voltage for the VCO is nominally somewhat centered within its expected voltage range.
One possible technique increases the gain of the VCO so that large changes in VCO frequency may be achieved by changes in the control voltage well within the expected range of control voltages. In principle this would allow a PLL to compensate for a large deviation in VCO xe2x80x9ccenter frequencyxe2x80x9d without requiring a control voltage dangerously close to xe2x80x9crunning out of range.xe2x80x9d But there are detrimental consequences of increasing the VCO gain, including danger of locking onto a harmonic, and increased noise and jitter of the system. Moreover, with most VCO circuit structures it is difficult to arbitrarily provide an ever higher and higher tuning range and still achieve good frequency and phase stability.
One approach to accommodating the VCO center frequency variations involves trimming the frequency using, for example, a precision laser. After the semiconductor fabrication steps are complete, and either during wafer-level testing or possibly after singulization of individual circuit dies, the VCO is tested to determine its center frequency, and various circuit elements (e.g., resistors, capacitors) are trimmed to adjust the center frequency to the desired value. The remaining testing and packaging operations are then performed to complete the manufacturing of the circuits. Alternatively, such trimming may also be accomplished using a flash memory programming technique coupled with appropriate selection circuits, although this requires a semiconductor process capable of forming compatible flash memory elements. In either case, such trimming is a xe2x80x9cpermanentxe2x80x9d adjustment of the center frequency during manufacture, but it adds costly manufacturing steps to either accomplish laser trimming after wafer fabrication or to provide a semiconductor process capable of implementing flash memory structures or other kinds of programmable structures. Moreover, such trimming is performed once during manufacture, and cannot adjust for subsequent changes in environmental conditions that the circuit may be called upon to operate under.
Another approach to accommodating the VCO center frequency variations involves calibrating the VCO center frequency each time the circuit is powered-up. Such techniques may involve comparing the center frequency against an externally provided reference frequency signal and setting a number of storage elements (e.g., registers) to appropriately adjust the center frequency. Such storage elements are volatile and lose stored data when the circuit loses power. An example of a device that performs such a calibration upon power-up is the Si4133G RF Synthesizer, which is available from Silicon Laboratories, Inc. based in Austin, Tex.
These approaches are valuable additions to the state of the art, but they cannot accommodate variations in the center frequency as environmental conditions change, as semiconductor parameters drift over time (e.g., threshold voltage shifts), or as other artifacts of component aging occur. This becomes increasingly more important in certain industrial systems which are put into operation and virtually never shut down. Examples include various interface circuits within the telecommunications infrastructure, which may operate for years without an opportunity to recalibrate during a subsequent power-up operation.
What is needed is an effective way to accommodate environmental or parametric changes in a feedback system which occur after the system is powered up and while operational, without negatively impacting the operation of the feedback system within its intended specifications.
Such a capability may be accomplished in a clock and data recovery circuit, such as PLL 100, by introducing a second feedback loop which reacts to the control voltage reaching a level sufficiently different from its mid-range value by slowly adjusting additional tuning elements which, along with the tuning elements controlled by the control voltage signal, control the VCO frequency. Absent the first traditional feedback loop, a change in the VCO frequency would result, but the second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first feedback loop is able to compensate for the would-be change by adjusting the control voltage quickly enough in a direction toward the mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop may advantageously incorporate one or more digital control signals to affect a tuning change by changing from one state to another state. These digital signals preferably change no more than one bit at a time, and the single bit which changes is preferably caused to achieve a controlled transition time (or ramp rate) which is slow enough to cause a very gradual change in the value of the associated tuning elements. As a result, the PLL maintains lock during and after the digital signal changes state, and more importantly, maintains its phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance and jitter generation are not negatively impacted.
In a broader context of the present invention, such a capability may be accomplished in an electronic feedback system having a first feedback loop responsive to a control signal for controlling an operational parameter of the feedback system, by providing a second feedback loop for generating at least one digital control signal to influence the feedback system in a manner which, absent the first feedback loop, would result in a change to the controlled parameter when the digital control signal changes value. The digital control signals are arranged to influence the feedback system slowly enough, relative to the first feedback loop, to allow the first feedback loop to adjust the control signal and maintain the controlled parameter substantially unchanged as the digital control signal changes value.
In one aspect the invention provides a controlled resistance circuit forming a resistance between a first node and a second node having a controlled magnitude proportional to a reference resistance. The circuit includes a first variable resistance circuit connected between the first node and the second node, having an analog portion responsive to an analog control signal and having a digital portion responsive to a digital control signal, and whose magnitude is responsive to both the analog control signal and the digital control signal. The circuit also includes a second variable resistance circuit connected between a third node and a fourth node, having an analog portion responsive to the analog control signal and having a digital portion responsive to the digital control signal, and whose magnitude, for a given value of the analog control signal and a given value of the digital control signal, is proportional to the magnitude of the first variable resistance circuit. A first feedback circuit is responsive to a voltage developed across the second variable resistance circuit by a controlled first current flowing therethrough, for generating the analog control signal accordingly to adjust the magnitude of the second variable resistance circuit toward a magnitude which is proportional to the reference resistance. A second feedback circuit is responsive to the analog control signal when the analog control signal is driven outside a predetermined range, for generating the digital control signal to accordingly further adjust the magnitude of the second variable resistance circuit in like direction as that resultant from the analog control signal being driven outside the predetermined range, so that the first feedback circuit drives the analog control signal back within the predetermined range. The first and second feedback circuits are preferably arranged to generally maintain the analog control signal within the predetermined range and to adjust the magnitude of the second variable resistance circuit to a magnitude proportional to the reference resistance, thereby likewise adjusting the magnitude of the first variable resistance circuit to a controlled magnitude which is proportional to the reference resistance.
The reference resistance may be a resistor external to an integrated circuit upon which the controlled resistance circuit is implemented, but may also be integral to an integrated circuit upon which the controlled resistance circuit is implemented, and may further be trimmable during manufacture or testing of the integrated circuit.
In yet another aspect the invention provides a resistance circuit providing a resistance between a first node and a second node having a controlled magnitude proportional to a reference resistance. The resistance circuit includes a first variable resistance circuit connected between the first node and the second node, having a magnitude that is responsive to at least one control signal. The resistance circuit includes a second variable resistance circuit connected between a third node and a fourth node, having a magnitude that is responsive to the at least one control signal and which magnitude, for a given value of the at least one control signal, is proportional to the magnitude of the first variable resistance circuit. A bias circuit includes a first bias resistance, and generates a controlled reference current and a controlled bias current, wherein a ratio of the controlled bias current to the controlled reference current is proportional to the ratio of the reference resistance to the first bias resistance. The resistance circuit includes a second bias resistance having a magnitude which is proportional to that of the first bias resistance and which is implemented to track variations in the first bias resistance. A feedback circuit is arranged to compare a first voltage developed across the second bias resistance by the controlled bias current flowing therethrough against a second voltage developed across the second variable resistance circuit by the controlled reference current flowing therethrough, and to generate accordingly the at least one control signal to adjust the value of the second variable resistance circuit so that the first voltage substantially equals the second voltage, thereby resulting in the second variable resistance circuit having a magnitude proportional to the reference resistance. The first variable resistance circuit, being also responsive to the at least one control signal, likewise achieves a magnitude proportional to the reference resistance.